1. Field of the Invention
The present invention relates generally to electronic circuits and, more particularly, to a voltage level translator for electrical devices.
2. Related Art
A semiconductor device or an integrated circuit device (ICxe2x80x94also referred to as a chip) often requires several regulated voltages to interface among internal circuits or with external circuits or devices operating at different voltage levels. For example, an IC may require one supply voltage level for operating its internal core logic or circuits and one or more different supply voltage levels to interface input/output (I/O) signals with external devices that operate at different supply voltage levels. The voltage levels of the interface I/O signals may vary, as an example for a mixed-voltage system, from 1.4 to 5.0 volts, depending upon the selected interface.
A voltage level translator permits an IC to operate in a mixed-voltage system or have circuits operating at different voltage levels by providing the necessary translation from one voltage level to another voltage level. As an example for the mixed-voltage system, the IC""s I/O interface signals, which may have strict timing parameters, are translated by the voltage level translator from one voltage level to the voltage level required by the I/O interface prior to being driven onto a bus or similar interface structure.
FIG. 2 illustrates an exemplary conventional voltage level translator 200. A drawback of conventional voltage level translators is their slow voltage level translation speed and their inability to function well over a wide range of output voltage levels that may be greater than or less than the core voltage level of the IC. As a result, there is a need for a high-speed voltage level translator, which operates over a wide range of voltage levels.
In accordance with some embodiments of the present invention, an improved voltage level translator is provided that operates over a wide range of voltage levels at a fast translation speed. Furthermore, in some embodiments, the die area (i.e., the amount of silicon space) required by the voltage level translator is less than or equal to conventional voltage level translators.
In accordance with one embodiment of the present invention, a voltage level translator includes an input terminal that receives an input signal and a capacitor having a first terminal coupled to the input terminal and to a first terminal of an output buffer. The output buffer has its second terminal coupled to the second terminal of the capacitor. The voltage level translator further includes a clamp circuit and a voltage source circuit and may optionally include a safeguard circuit. The clamp circuit couples to the input terminal and to the second terminal of the capacitor to provide a signal on the second terminal of the capacitor in response to a first voltage level of the input signal. The voltage source circuit couples to the clamp circuit and to the second terminal of the capacitor to provide a signal on the second terminal of the capacitor in response to a second voltage level of the input signal. The safeguard circuit couples to the input terminal, to the clamp circuit, and to the voltage source circuit, and ensures that the clamp circuit and the voltage source circuit are enabled or disabled appropriately based on certain voltage levels of the input signal, regardless of the initial charge on the capacitor during power-up. The output buffer provides an output signal having a translated voltage level on its output terminal in response to signals on the first and second terminals of the capacitor.
In accordance with another embodiment of the present invention, a method includes receiving an input signal having a first and second voltage level; generating a signal having a third or fourth voltage level at a first terminal of a capacitor in response to respective first or second voltage levels of the input signal, with a second terminal of the capacitor receiving the input signal; and providing a translated output signal in response to voltage levels at the first and second terminal of the capacitor.
A more complete understanding of the present invention will be afforded to those skilled in the art, as well as a realization of additional advantages thereof, by a consideration of the following detailed description of one or more embodiments. Reference will be made to the drawings that will first be described briefly.